The clock in FPGAs: Edges, synchronism, and maximum frequency

The clock is the periodic signal that coordinates when registers change state inside a digital circuit.

Up to this point in the course, we have designed purely combinational circuits. AND gates, OR gates, multiplexers… In these circuits, if you change the input, the output changes “instantly” (as fast as electrons can cross the silicon).

The real world is not static. We need to remember the past (memory) and coordinate actions (sequence).

To achieve this, we need a conductor to set the rhythm. We need the most important signal in the entire FPGA: The Clock.

Today we enter the domain of Sequential Logic.

What is the clock?

Imagine an orchestra with 100 musicians. If each one plays their note as fast as they can, the result would be chaotic noise. They need a conductor to move the baton. No one plays the next note until the conductor gives the signal.

In an FPGA, the Clock (clk) is that baton. It is an electrical signal (square wave) that constantly oscillates between 0 and 1 at a fixed speed (Frequency).

• Low Level (0): The circuit “rests”.
• High Level (1): The circuit “rests”.
• The Change (Edge): ACTION!

The rising edge (posedge)

In Verilog, you will constantly see this instruction:

always @(posedge clk)

posedge means Positive Edge. It is the infinitesimal instant when the signal transitions from 0 to 1.

Why do we use the edge and not the level? Because the edge is a punctual event. It defines an exact “now”. If we used the level (while clk is 1), the signal would be active for a long time (nanoseconds), and during that time, electrons could travel around the circuit multiple times, causing chaos and instability.

By using the edge, we take a “snapshot” of the input state at that precise instant and update the outputs.

Synchronism and stability

We say a part of the design is synchronous when its memory elements are coordinated by a clock signal. A system can contain multiple clock domains, but signals crossing between them require specific treatment.

This allows registers to not capture intermediate glitches as long as the signals stabilize in time.

The problem of glitches

Imagine you have an addition A + B. If A changes from 0 to 1 one nanosecond before B, the sum output might momentarily give an erroneous value before stabilizing. If you connected that unstable output to another circuit, the error would propagate like a snowball.

The synchronous solution

In a synchronous design, we don’t care what happens between the tick and tock of the clock.

1. Tick (Edge): Data leaves the registers.
2. Flight time: Data travels through the logic gates (adders, muxes…). During this time, the wires have “garbage” or transient values.
3. Tock (Next Edge): By the time the next edge arrives, the signals have stabilized. The registers capture the clean, correct result.

Implementation in Verilog

Let’s see the visual difference between a combinational circuit (without clock) and a sequential one (with clock).

Combinational circuit

This block is triggered if a or b changes. The output changes immediately.

// Combinational Logic (No memory)
always @(a or b) begin 
// Or better: always @(*)
    y = a & b;
end

Sequential circuit

This block is triggered only when the clock rises. It doesn’t matter if a or b change a thousand times in the middle of the cycle; the circuit ignores them until the edge arrives.

// Sequential Logic (Memory / Synchronous)
always @(posedge clk) begin
    y <= a & b; // We use non-blocking assignment
end

Maximum frequency (Fmax)

This leads us to a key engineering concept. How fast can we go?

If we use a 1 GHz clock, the time between edges is 1 nanosecond. If our logic (the additions and multiplications) takes 2 nanoseconds to compute the result, when the next edge arrives the data will not be ready yet. We will capture garbage.

The Timing Analysis of the toolchain calculates exactly this:

• Critical Path: The longest path between two Flip-Flops.
• Maximum Frequency: The speed limit before the circuit fails.