The architecture of an FPGA is a matrix of logic blocks connected by programmable interconnects. By configuring both resources, the same chip can behave as a processor, a video controller, or many other digital circuits.
To understand how it manages to change circuits, we need to take a scalpel and look inside the silicon. Broadly speaking, we will see a large number of “islands” of programmable logic surrounded by a sea of configurable connections.
These “islands” are often called Logic Cells or Logic Elements (LE), and inside them we find the two main characters of our story: the LUT and the Flip-Flop.
Although each manufacturer (Xilinx/AMD, Intel/Altera, Lattice) uses slightly different trade names (CLB, LAB, Slice), the underlying concept is identical in 99% of modern FPGAs.
The LUT (Look-Up Table)
The LUT (Look-Up Table) is a small memory that implements a logic function based on its truth table.
When you study classic digital electronics, you learn about logic gates: AND, OR, NOT, XOR, NAND… You might think that inside an FPGA there are millions of these tiny gates waiting to be connected. Well, no.
An FPGA does not present the designer with a collection of individual AND and OR gates. Instead, it uses configurable LUTs to implement most combinational functions.
How does a LUT work?
Imagine a LUT as a small RAM memory. If we want to implement a 2-input AND gate, we don’t build the AND gate circuit. What we do is store its truth table in the LUT’s memory.
| Input A | Input B | Output (Stored in LUT) |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
When the inputs change, the LUT simply “looks up” in its memory what value to return for that combination.
By changing the values stored in this small memory, the same physical structure can behave as an AND, an OR, an XOR, or any complex logic function you can imagine.
Physically, a LUT is built using Multiplexers and SRAM memory cells. A typical modern LUT usually has 4 or 6 inputs (LUT4 or LUT6). A single LUT6 can implement any boolean function of up to 6 variables.
The D-Type Flip-Flop
If the LUT is the brain that calculates, the Flip-Flop is the memory that remembers.
Combinational logic (the LUTs) is instantaneous and ephemeral. As soon as the inputs change, the output changes. But to build complex systems (counters, state machines, CPUs), we need to retain information and synchronize it with time.
For this, right at the output of each LUT, we find a D-Type Flip-Flop.
The Flip-Flop captures the output value of the LUT only when a clock signal arrives (the famous Clock).
The Output Multiplexer (Bypass)
Inside the logic cell, we usually have a small multiplexer that allows us to choose what goes out to the rest of the chip:
- The direct output of the LUT (Pure Combinational Logic).
- The output registered by the Flip-Flop (Sequential Logic).
This gives us total flexibility to design synchronous or asynchronous circuits as needed.
Routing or Programmable Interconnect
We now have the logic cells that calculate and store data. Now, how do we connect the output of cell 1 to the input of cell 500?
This is where the Routing Fabric or interconnection matrix comes in.
If we look at the chip under a microscope, we will see that most of the area is not LUTs, but wires and switches. It’s like a massive telephone exchange.
The FPGA software is responsible for activating or deactivating thousands of pass transistors to create electrical “paths” between different logic blocks.
Routing is generally the most critical resource. Poor routing can make your design slow because the signal takes too long to travel from one side of the chip to the other (Timing issues).
Other Blocks (Hard IP)
If FPGAs only had LUTs and Flip-Flops, they would be very flexible but inefficient for certain heavy tasks. Therefore, manufacturers include specialized silicon blocks, known as Hard IP (Intellectual Property).
These blocks are already physically “fabricated” (like in an ASIC) and we only configure them. They are much faster and more efficient than trying to do the same thing by combining thousands of LUTs.
The most common ones are:
Block RAM (BRAM)
These are dedicated RAM memory blocks whose size depends on each family (e.g., 4 Kbit or 36 Kbit per block). They are very useful for making video buffers, FIFO queues, or small processor memories.
DSP Blocks (Digital Signal Processing)
These are hardware multipliers. A LUT is very poor at multiplying large numbers. DSP blocks can perform operations like A * B + C in a single clock cycle at blazing speeds. They are the reason FPGAs dominate in radar, audio, and telecommunications.
PLL and MMCM for Clock Management
Analog and digital blocks that allow taking the input clock (e.g., 12 MHz) and multiplying it, dividing it, or shifting its phase to generate other clocks.
How the Blocks Fit Together
We can summarize a generic logic cell with this mental diagram:
- Signals enter.
- They pass through a LUT (which decides what logic function to apply).
- The result can be stored in a Flip-Flop (to synchronize with the clock).
- It exits through the Routing matrix to another cell.
Understanding this is important because, when we write code in Verilog, we will not be giving orders to a processor. We will be describing how to connect these little boxes.
