VGA and HDMI Video Generation with FPGA

module vga_driver (
    input wire clk_25mhz,   // Exact pixel clock
    input wire rst,
    output wire hsync,      // VGA H-Sync pin
    output wire vsync,      // VGA V-Sync pin
    output wire video_on,   // 1 = We are in the visible area
    output wire [9:0] x,    // Current X coordinate (for other modules to paint)
    output wire [9:0] y     // Current Y coordinate
);

    // Standard VGA 640x480 60Hz parameters
    localparam H_VISIBLE = 640;
    localparam H_FRONT   = 16;
    localparam H_SYNC    = 96;
    localparam H_BACK    = 48;
    localparam H_TOTAL   = 800; // 640+16+96+48

    localparam V_VISIBLE = 480;
    localparam V_FRONT   = 10;
    localparam V_SYNC    = 2;
    localparam V_BACK    = 33;
    localparam V_TOTAL   = 525; // 480+10+2+33

    // Counters
    reg [9:0] h_count = 0;
    reg [9:0] v_count = 0;

    // 1. Horizontal and Vertical Counter
    always @(posedge clk_25mhz) begin
        if (rst) begin
            h_count <= 0;
            v_count <= 0;
        end else begin
            // Horizontal advance
            if (h_count == H_TOTAL - 1) begin
                h_count <= 0;
                // Vertical advance (at the end of a line)
                if (v_count == V_TOTAL - 1) begin
                    v_count <= 0;
                end else begin
                    v_count <= v_count + 1;
                end
            end else begin
                h_count <= h_count + 1;
            end
        end
    end

    // 2. Sync pulses active low and aligned with counters
    assign hsync = ~((h_count >= H_VISIBLE + H_FRONT) &&
                     (h_count <  H_VISIBLE + H_FRONT + H_SYNC));
    assign vsync = ~((v_count >= V_VISIBLE + V_FRONT) &&
                     (v_count <  V_VISIBLE + V_FRONT + V_SYNC));

    // 3. Video ON signal (Only paint when in the visible area)
    assign video_on = (h_count < H_VISIBLE) && (v_count < V_VISIBLE);

    // 4. Export coordinates for the drawing logic
    assign x = h_count;
    assign y = v_count;

endmodule

module test_patron (
    input wire clk,         // 12 MHz input (if using external PLL) or 25 MHz
    output wire hsync,
    output wire vsync,
    output wire [2:0] rgb   // 3 pins: R, G, B (1 bit each)
);

    wire video_on;
    wire [9:0] x, y;

    // Instance of the VGA driver (Assuming 'clk' is already 25 MHz)
    vga_driver mi_vga (
        .clk_25mhz(clk),
        .rst(1'b0),
        .hsync(hsync),
        .vsync(vsync),
        .video_on(video_on),
        .x(x),
        .y(y)
    );

    // PAINT LOGIC
    // If video_on is 0, it is MANDATORY to send BLACK (000).
    // Otherwise, the monitor will lose the black level and display poorly.
    
    reg [2:0] color_pintar;
    
    always @(*) begin
        if (!video_on) begin
            color_pintar = 3'b000;
        end else begin
            // Example: Vertical tricolor flag
            if (x < 213)      color_pintar = 3'b100; // Red
            else if (x < 426) color_pintar = 3'b010; // Green
            else              color_pintar = 3'b001; // Blue
            
            // Example 2: Chessboard pattern
            // color_pintar = (x[4] ^ y[4]) ? 3'b111 : 3'b000;
        end
    end

    assign rgb = color_pintar;

endmodule