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What is a Softcore Processor: MicroBlaze V, Nios V and RISC-V

  • 5 min

A softcore processor is a CPU implemented using the programmable resources of an FPGA instead of using a dedicated silicon core.

So far we’ve been thinking like hardware designers: connecting wires, creating counters and state machines. All very nice. But it won’t always be like this… sometimes pure hardware is a headache.

Imagine you want to implement a TCP/IP stack to connect to the internet, or parse a JSON file from an SD card. Doing that with state machines in Verilog is a titanic and error-prone task. Those tasks are trivial for a processor running C or C++.

What if we could have the best of both worlds? What if we could create our own processor inside the FPGA?

Welcome to the world of Softcores.

What is a softcore?

A Softcore (or Soft Processor) is a CPU that does not physically exist as dedicated silicon.

It is a processor described using an HDL like Verilog or VHDL. It’s just another module, like our counters or VGA controllers, though much more complex. When synthesized, the tool uses LUTs, flip-flops, and BRAM memory to implement a functional microprocessor.

Difference from a hard core

  • Hardcore: It’s a physical chip (like the ATmega328 in an Arduino or the ARM cores inside a Zynq/Raspberry Pi). Its transistors are fixed at the factory. It’s very fast and power-efficient, but you cannot change it.
  • Softcore: It is “programmed logic”. It is slower than a dedicated silicon chip (generally running between 50 MHz and 200 MHz), but it is completely flexible.

If tomorrow you need your processor to have 3 UART ports, 5 SPI, and a hardware cryptography module, with a Softcore you simply reconfigure the design and you have it. On a microcontroller, you would have to change the chip and redesign the PCB.

Why use a softcore in an FPGA?

You might think: “If the beauty of the FPGA is parallelism, why would I want to put a sequential and slow CPU inside?”.

The answer is the Hybrid Architecture.

In a complex design, we usually divide the tasks:

  1. Hardware (Pure FPGA): Critical, repetitive, and high-speed tasks. (e.g., Video processing, signal filtering, PWM motor control, encryption).
  2. Software (Softcore): Management tasks, complex business logic, and communication. (e.g., User menus, file management, network communication, slow decision-making).

The Softcore acts as the “General Manager”, sending orders to the accelerated hardware modules that do the heavy lifting.

Softcores integrated by manufacturers

Manufacturers offer cores and peripherals that are highly integrated with their tools. This integration simplifies SoC creation, although the hardware IP and the flow are usually tied to a specific family.

MicroBlaze and MicroBlaze V (AMD)

The classic MicroBlaze uses AMD’s proprietary ISA. MicroBlaze V, on the other hand, is the current generation based on RISC-V and supports RV32 and RV64 configurations with optional extensions. It integrates with Vivado and Vitis and can be used at no additional cost in compatible AMD devices, but the IP is still oriented towards that ecosystem.

Nios V (Altera)

Nios II was the option for the Intel/Altera ecosystem for years, but it is now in legacy support. For new designs, the manufacturer recommends Nios V, also based on RISC-V.

This change is important: RISC-V improves software portability, although moving an entire SoC still requires adapting the memory map, peripherals, and hardware integration.

The open ISA RISC-V

A few years ago, researchers at the University of Berkeley created something that changed the industry forever: RISC-V (pronounced “Risk-Five”).

RISC-V is not a processor, it is an open and free ISA (Instruction Set Architecture). It’s like a manual that says: “If you find the binary code 0000001, you must add two numbers”.

Anyone is free to design a processor that understands these instructions, without paying royalties to anyone (unlike ARM or x86).

Why RISC-V fits well in an FPGA

  1. Software portability: The same source code can be compiled for different cores. A binary will only be compatible if the ISA, extensions, ABI, and runtime environment match.
  2. Community: There are dozens of Open Source cores ready to use (PicoRV32, VexRiscv, NEORV32, Ibex…).
  3. Free Tools: We use standard GCC and GDB. We don’t depend on heavy proprietary IDEs.

Components of a SoC with a softcore

For the processor to be useful, the CPU alone is not enough. We need to create a small computer inside the FPGA. This is called an SoC (System on Chip).

It typically consists of:

  1. Core: The CPU that executes instructions.

  2. System Bus: The data “highway”. It connects the CPU to the peripherals.

    • In the open-source world, Wishbone or AXI is widely used.
  3. Memory:

    • ROM/BRAM: To store the program (Bootloader).
    • RAM: For data and variables.
  4. Peripherals:

    • Timer: For timekeeping.
    • UART: For printf and debug.
    • GPIO: To turn on LEDs and read buttons.

The cool thing is that these peripherals are Memory Mapped IO. For the CPU, turning on an LED is simply writing a value to a reserved memory address (e.g., 0x80000000). The bus takes care of routing that data to the Verilog module for the LED.